1. Field of the Invention
The present invention relates to a data processing apparatus comprising a central processing unit and peripheral devices with different data bus widths.
2. Description of the Prior Art
A data processing apparatus according to the prior art is described below with reference to FIG. 8. FIG. 8 is a block diagram of the data processing apparatus disclosed in U.S. Pat. No. 4,447,878. In FIG. 8, reference numerals each 65 and 66 denote a 16-bit data bus; numerals 67 and 68 denote an 8-bit data bus constituted by the lower 8 bits of a 16-bit data bus; numerals 69 and 70 denote an 8-bit data bus constituted by the upper 8 bits of a 16-bit data bus; numerals 71, 72, 73 and 74 each denote an 8-bit bus transceiver; numerals 76 to 79 each denote an 8-bit I/O peripheral device; numeral 80 denotes a 16-bit I/O central processing unit and numeral 75 denotes a 16-bit I/O peripheral device. The 8-bit bus transceivers 71 to 74 are devices for relaying data transmission by connecting two 8-bit data buses and a direction of data transmission and transmission state or off state of each of them are controlled by a control line.
It is to be noted that the term "line" is often used to indicate a bundle of lines in this specification.
FIG. 9 is a circuit of the 8-bit bus transceiver. When a logic value "H" is input to a control line /OE, the outputs of all the buffer gates are placed in their high resistive states and accordingly, each of the output terminals Y0 to Y7 is disconnected from each of the input terminals X0 to X7. When a logic value "L" is input to the control line/OE and a logic value "H" is input to another control line DIR, each of the buffer gates directing from the X side to the Y side is placed in an output enable state and the data input to the terminals X0 to X7 are thereby transmitted to the output terminals Y0 to Y7. When a logic value "L" is input to the control line/OE and a logic value "L" is input to the control line DIR, each of the buffer gates directing from the Y side to the X side is brought into an output enable state and data is transmitted from the terminals Y0 to Y7 to the terminals X0 to X7. 8-bit bus transceivers of this type are supplied as SN74AS245.RTM. by Texas Instrument Inc. and second source makers thereof.
Next, the operation of the data processing apparatus shown in FIG. 8 is explained below.
In a case where a data transmission is effected between any two arbitrary 8-bit I/O peripheral devices 76 to 79, the 8-bit data bus 68 is used. In a case where a data transmission is effected between the CPU 80 and any one of the 8-bit I/O peripheral devices 76 to 79, data paths are switched in accordance with whether each of addresses allocated to the respective data is odd or even since the position of the data to be processed in the CPU is altered from an upper byte to a lower byte or vice versa in accordance therewith. Namely, upon transmitting data of an even address, a data path constituted by 8-bit data buses 67 and 68 and 8-bit bus transceiver 71 is selected and a lower byte is used to process data in the CPU 80. In the case of an odd address data, data is transmitted through a data path constituted by the 8-bit data buses 69 and 68 and the 8-bit bus transceiver 73 and an upper byte is used to process data therein. If another bus transceiver 74 is used instead of transceiver 73, data transmission is effected through a data path constituted by the 8-bit data buses 69, 67 and 68 and the 8-bit bus transceivers 74 and 71. To transmit data between the CPU 80 and the 16-bit I/O peripheral device 75, a data path constituted by two 16-bit data buses 65 and 66 and two 8-bit bus transceivers 71 and 72 is used. In a case where the CPU 80 transmits 16-bit data to any one of the 8-bit I/O peripheral devices 76 to 79, two 8-bit data units divided from one 16-bit data unit are sequentially transmitted. The case of a (2.times.8)-bit data bus is explained above; however, a (4.times.8) or (2.times.16) bit data bus is available in a manner similar to the above.
However, the conventional apparatus mentioned above has the following problems to be solved. Since all of the 8-bit peripheral devices are connected to the 8-bit data bus 68 corresponding to the lower byte, electrical loads are concentrated with driving circuits which drive data buses of the devices connected to the 8-bit data bus of the lower byte. The circuits which drive the 8-bit data buses of the lower byte are 8-bit I/O peripheral devices, 16-bit I/O peripheral devices and 8-bit bus transceivers. Due to this, the number of connectable 8-bit and/or 16-bit I/O peripheral devices is restricted. In the following, a device for driving each data bus such a CPU, peripheral device, 8-bit bus transceiver or register is referred to as a data bus driving device. In order to reduce the electrical load of each data bus driving device, it is considered that 8-bit peripheral devices are grouped into two in such a manner that each of two groups gives a substantially equal load to either of two 8-bit data buses corresponding to upper and lower bytes of the 16-bit data bus. However, a mere change in the connection relationship from one 8-bit data bus to another needs a relay using the CPU to transmit data between 8-bit peripheral devices of upper and lower bytes and control programs become complex since 8-bit data exists in two ways of upper and lower bytes.
Furthermore, in the conventional data processing, the member of machine cycles of the CPU is increased when the CPU transmits 16-bit data to an 8-bit I/O peripheral device since the data must be sequentially transmitted in 8 bit units in two time periods.